1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a sensing circuit for a semiconductor device and a sensing method using the same, which allows sensing of a selected nonvolatile memory cell at a low voltage, a low power, and a fast speed, and has a high sensing reliability.
2. Background of the Related Art
A related art sensing circuit for a semiconductor device will be explained with reference to the attached drawings. FIG. 1 illustrates a first exemplary related art sensing circuit for a semiconductor memory, and FIG. 2 illustrates a second exemplary related art sensing circuit for a semiconductor memory.
Referring to FIG. 1, the first exemplary related art sensing circuit for a semiconductor memory is provided with a memory cell(for example, a nonvolatile EEPROM) connected to, and selected both by a wordline and a bitline, a bitline capacitor Cb1 parasitically present between the bitline and a ground voltage terminal Vss, a Y-decoder between the bitline to the memory cell and a sensing node, a PMOS transistor between a source voltage terminal and the sensing node responsive to a reference voltage Vref(or a bias voltage Vbias), and a buffer for sensing a signal from the sensing node.
Referring to FIG. 2, the second exemplary related art sensing circuit for a semiconductor memory is provided with a memory cell(for example, a nonvolatile EEPROM) selected both by a wordline and a Y-decoder connected to a bitline, a bitline capacitor Cb1 parasitically present between the bitline and a ground voltage terminal Vss, the Y-decoder and a voltage clamping unit connected in series between the bitline of the memory cell and the sensing node, PMOS transistor between a source voltage terminal Vdd and the sensing node having a gate terminal connected to a drain terminal, a comparing unit for comparing a voltage on the sensing node to a reference voltage Vref. The voltage clamping unit, provided for clamping a bitline voltage, is provided with a buffer for forwarding a signal decoded in the Y-decoder and an NMOS transistor responsive to the buffer output.
The operations of the aforementioned related art sensing circuits for a semiconductor memory will be explained.
Referring to FIG. 1, in the first exemplary related art sensing circuit for a semiconductor memory, the reference voltage is applied to the bitline to the memory cell, for sensing a programmed, or erased state by boosting or dropping a bitline voltage. In the erased state, the channel has a low Vth to allow an adequate current flow when a V.sub.W/L is applied. And, in the programmed state, the channel has a high Vth not to allow a current flow when a V.sub.W/L is applied. For example, when the memory cell is at an erased state, i.e., when the memory cell has a low Vth, upon application of a voltage of V.sub.W/L to the memory cell selected by the Y-decoder, a `high` level is sensed due to drop of the sensing node voltage caused by flow of a current greater than the reference current flowing into the sensing node through the PMOS transistor coming from the low Vth. A value of a memory cell voltage level is provided. Opposite to this, when the memory cell is programmed, a `low` level value is provided.
In the second exemplary related art sensing circuit for a semiconductor memory provided for supplementing drop of a sensing reliability due to changed bitline voltage caused by a memory cell current during sensing operation in the first exemplary related art sensing circuit for a semiconductor memory, the bitline to the memory cell selected by the Y-decoder is adjusted of its voltage to an arbitrary level through a negative feed back loop, i.e., a voltage clamping unit, a cell current flowing through a selected bitline is converted into a voltage form, and compared with a reference voltage using a comparing unit, to sense a memory cell state. For example, when the memory cell is at an erased state, the NMOS transistor in the voltage clamping unit is turned on and quickly becomes responsive to the sensing node, because current is drained through the memory cell, a voltage lower than the reference voltage Vref is generated, and, accordingly, a value at the sensing node is compared to the reference value, to provide a `high` sensing value. Opposite to this, when the memory cell is programmed, the NMOS transistor in the voltage clamping unit is turned off, to generate a voltage Vdd-.vertline.V.sub.THP.vertline., providing a `low` sensing value through the comparing unit.
However, the related art sensing circuits for a semiconductor memory have the following problems.
First, there have been a problem of soft programming caused by a relatively high voltage applied to a bitline in sensing a memory cell state, and problems of power consumption and a speed drop caused by charging and discharging of a bitline capacitance due to a great voltage swing.
Second, despite the comparatively low voltage level clamping of the bitline voltage in the second exemplary related art sensing circuit for a semiconductor memory, the second exemplary related art sensing circuit for a semiconductor memory is involved in additional power consumption due to the reduced cell current and increased components, has difficulty in embodiment of the same in an environment requiring a low voltage and a low power, and has a low fabrication process reproducibility.